The multi-priced venture funding systems and methods described herein allow for increasing the pace of investment and stabilizing private equity funding rounds so that raising capital can be more efficient and provide more equitable assumption of risk. The multi-pricing allows investors to tailor their risk tolerance by providing a measure of reward for investing early and assuming more risk. Later investors, knowing that a certain amount of funding has already been obtained from early investors, can be encouraged to invest with some assurance that the venture will be adequately funded.

The multi-priced venture funding comprises a plurality of two or more price categories wherein tranches of price categories are sequentially offered at incrementally increasing prices, wherein each tranche is calculated to raise a known percentage of a target valuation to be raised. Preferably the price of each tranche increases over the previous tranche. Figure 1A illustrates a model multi-priced venture funding regime comprising two tranches of price categories. In this example, the first price category may be initially offered at $100 per share and the second price category is offered at $130 per share. The amount of shares in the price categories may be the same or different. The percentage of revenue raised by each tranche may also be the same or different.

Preferably, the issue of securities, for example the total number of shares, is divided into three to five (or more) tranches, as illustrated in Figure 1B. In this embodiment, the price per share of the tranches increases at roughly 30% increments, rising from $100 per share in the first tranche to $300 per share. In some embodiments such as shown in Figure 1B, the number of shares and the price per share increase in the tranches may be relatively fixed.

In other embodiments, the percentage of price increase and the number of shares may be variable. For example, in embodiments, the number of shares and the price increase may be fixed in the first four tranches, while the fifth tranche may have a significantly higher number of shares than the other tranches and a significantly higher price per share. This embodiment may be used when the offering is particularly popular, allowing for many investors to invest in the offering once a threshold level funding is attained in the early tranches. Figure 1C shows an embodiment wherein the first four tranches have a price increase of 30 % at each tranche, while the price increase between the fourth and fifth tranches is 167%, from $225 to $600 per share.

Splitting the offering into a plurality of tranches may incentivize early investing, where the rewards of early investing translate into a higher percentage of holdings in the company. For example, shares in the first tranche may be weighted to give early investors a higher percentage of shares in the venture than later tranches. This may encourage investors to bid up the first tranche price to ensure that they get a preferred position compared to investors in the later tranches.

When a new tranche is sold, the investors who invested in a previous tranche that want or need to exit can sell some or all of their securities at a profit to new investors at the same new price or slightly below. The main advantage is that if the company is mismanaged or could not achieve its initial objectives or is simply running out of money, new investors will still buy shares of stock at a higher price than the earlier investors who took the biggest risk. Early investors in the first tranche have some confidence that they may be able to exit the venture by selling to later investors at a profit.

To manage their risk, investors may invest all their capital in one tranche or may spread their capital into multiple tranches. For example, early investors in the first tranche may also buy more shares in subsequent tranches as others also invest. Other investors may want to wait until later tranches are offered, so that they have assurance that the venture is adequately funded by the earlier tranches.

As shown in FIG. 2, a computer system 200 is the core element of this financing method, generating, storing, integrating and coordinating data required for planning, developing, modeling, evaluating, executing and administering offerings of securities. The computer system is further provided with a processor and into which is loaded a software component for receiving informational inputs relating to at least one investor and at least one a bank or other financial institution that organizes an issue of new shares for a venture.

In block 210, planning the offering of securities includes establishing the target amount of capital to be raised. Guided by inputs from administrator(s) of the system from a bank, broker, underwriter and/or other financial institutions, the system conducts feasibility studies for offering of tranches of multi-priced shares to define the structure of the offering. The offering planning includes specific variables to be included, ranges of acceptable values for each variable, and terms and conditions to be included in the offering.

In block 220, the system models and projects multiple values of individual variables and combinations of multiple sets of variables, such as time series projections and economic modeling of interaction between variables.

In block 230, the system evaluates alternatives by reviewing results of modeling and projections. Selecting one or more sets of variables that meet targets will be used to refine the structure and value of variables and terms and conditions for price categories of the multi-priced shares. Additional modeling and projections may be required to define a preferred set of values for the variables and terms and conditions for inclusion in the offering of securities in the price categories of the multi-priced shares.

In block 240, the system executes the offering of the securities. The price and content of the individual shares of the price category tranches are established, including definitions of shares of revenues and assets to be included in each tranche. Technical and legal details are finalized and the tranches are brought to market. The system receives and accepts bids for shares in each tranche from at least one investor, tracks progress of sales of shares within each tranche, closes tranches when target values are met, and opens subsequent tranches. The system also receives sell orders from holders of shares from early tranches when subsequent tranches are opened and sells them to new investors.

In block 250, the system administers the securities (shares) in the offering. It maintains detailed and current records of individual investor accounts as required for periodic and cumulative payments, tax treatment, benefits, reports and other purposes. It maintains required and useful records related to financial analysis and financial reports of investors, brokers, and other involved parties.

FIG. 3 depicts a computer system 300 according to an embodiment of the present disclosure. In general, the computer system 300 may include a computing device 310, such as a special-purpose computer designed and implemented for receiving user inputs, determining and directing and controlling the output of signals. The computing device 310 may be or include data sources, client devices, and so forth. In certain aspects, the computing device 310 may be implemented using hardware or a combination of software and hardware. The computing device 310 may be a standalone device, a device integrated into another entity or device, a platform distributed across multiple entities, or a virtualized device executing in a virtualization environment.

The computing device 310 may communicate across a network 302. The network 302 may include any data network(s) or internetwork(s) suitable for communicating data and control information among participants in the computer system 300. This may include public networks such as the Internet, private networks, and telecommunications networks such as the Public Switched Telephone Network or cellular networks using cellular technology and/or other technologies, as well as any of a variety other local area networks or enterprise networks, along with any switches, routers, hubs, gateways, and the like that might be used to carry data among participants in the computer system 300. The network 302 may also include a combination of data networks and need not be limited to a strictly public or private network.

The computing device 310 may communicate with an external device 304. The external device 304 may be any computer, mobile device such as a cell phone, tablet, smart watch or other remote resource that connects to the computing device 310 through the network 302. This may include any of the servers or data sources described herein, including servers, content providers, databases or other sources for shot information to be used by the devices as described herein.

In general, the computing device 310 may include a controller or processor 312, a memory 314, a network interface 316, a data store 318, and one or more input/output interfaces 320. The computing device 310 may further include or be in communication with peripherals 322 and other external input/output devices that might connect to the input/output interfaces 320.

The controller 312 may be implemented in software, hardware or a combination of software and hardware. According to one aspect, the controller 312 may be implemented in application software running on a computer platform. Alternatively, the controller 312 may include a processor or other processing circuitry capable of processing instructions for execution within the computing device 310 or computer system 300. The controller 312, as hardware, may include a single-threaded processor, a multi-threaded processor, a multi-core processor and so forth. The controller 312 may be capable of processing instructions stored in the memory 314 or the data store 318.

The memory 314 may store information within the computing device 310. The memory 314 may include any volatile or non-volatile memory or other computer-readable medium, including without limitation a Random-Access Memory (RAM), a flash memory, a Read Only Memory (ROM), a Programmable Read-only Memory (PROM), an Erasable PROM (EPROM), registers, and so forth. The memory 314 may store program instructions, program data, executables, and other software and data useful for controlling operation of the computing device 310 and configuring the computing device 310 to perform functions for a user 330. The memory 314 may include a number of different stages and types of memory for different aspects of operation of the computing device 310. For example, a processor may include on-board memory and/or cache for faster access to certain data or instructions, and a separate, main memory or the like may be included to expand memory capacity as desired. All such memory types may be a part of the memory 314 as contemplated herein.

The memory 314 may, in general, include a non-volatile computer readable medium containing computer code that, when executed by the computing device 310 creates an execution environment for a computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of the foregoing, and that performs some or all of the steps set forth in the various flow charts and other algorithmic descriptions set forth herein. While a single memory 314 is depicted, it will be understood that any number of memories may be usefully incorporated into the computing device 310.

The network interface 316 may include any hardware and/or software for connecting the computing device 310 in a communicating relationship with other resources through the network 302. This may include remote resources accessible through the Internet, as well as local resources available using short range communications protocols using, e.g., physical connections (e.g., Ethernet), radio frequency communications (e.g., Wi-Fi, Bluetooth), optical communications (e.g., fiber optics, infrared, or the like), ultrasonic communications, or any combination of these or other media that might be used to carry data between the computing device 310 and other devices. The network interface 316 may, for example, include a router, a modem, a network card, an infrared transceiver, a radio frequency (RF) transceiver for receiving AM/FM or satellite radio sources, a near field communications interface, a radio-frequency identification (RFID) tag reader, or any other data reading or writing resource or the like.

The network interface 316 may include any combination of hardware and software suitable for coupling the components of the computing device 310 to other computing or communications resources. By way of example and not limitation, this may include electronics for a wired or wireless Ethernet connection operating according to the IEEE 802.11 standard (or any variation thereof), or any other short or long range wireless networking components or the like. This may include hardware for short range data communications such as Bluetooth or an infrared transceiver, which may be used to couple to other local devices, or to connect to a local area network or the like that is in turn coupled to a data network 302 such as the Internet. This may also include hardware/software for a WiMax connection or a cellular network connection (using, e.g., CDMA, GSM, LTE, or any other suitable protocol or combination of protocols). The network interface 316 may be included as part of the input/output devices 320 or vice-versa.

The data store 318 may be any internal or external memory store providing a computer-readable medium such as a disk drive, an optical drive, a magnetic drive, a flash drive, or other device capable of providing mass storage for the computing device 310. The data store 318 may store computer readable instructions, data structures, program modules, and other data for the computing device 310 or computer system 300 in a non-volatile form for relatively long-term, persistent storage and subsequent retrieval and use. For example, the data store 318 may store an operating system, application programs, program data, databases, files, and other program modules or other software objects and the like.

As used herein, processor, microprocessor, and/or digital processor may include any type of digital processing device such as, without limitation, digital signal processors (“DSPs”), reduced instruction set computers (“RISC”), complex instruction set computers (“CISC”) processors, microprocessors, gate arrays (e.g., field programmable gate arrays (“FPGAs”)), programmable logic device (“PLDs”), reconfigurable computer fabrics (“RCFs”), array processors, secure microprocessors, and application-specific integrated circuits (“ASICs”). Such digital processors may be contained on a single unitary integrated circuit die or distributed across multiple components.

As used herein, computer program and/or software may include any sequence or human or machine cognizable steps which perform a function. Such computer program and/or software may be rendered in any programming language or environment including, for example, C/C++, C#, Fortran, COBOL, MATLAB™, PASCAL, GO, RUST, SCALA, Python, assembly language, markup languages (e.g., HTML, SGML, XML, VoXML), and the like, as well as object-oriented environments such as the Common Object Request Broker Architecture (“CORBA”), JAVA™ (including J2ME, Java Beans, etc.), Binary Runtime Environment (e.g., “BREW”), and the like.

The input/output interface 320 may support input from and output to other devices that might couple to the computing device 310. This may, for example, include serial ports (e.g., RS-232 ports), universal serial bus (USB) ports, optical ports, Ethernet ports, telephone ports, audio jacks, component audio/video inputs, HDMI ports, and so forth, any of which might be used to form wired connections to other local devices. This may also include an infrared interface, RF interface, magnetic card reader, or other input/output system for wirelessly coupling in a communicating relationship with other local devices. It will be understood that, while the network interface 316 for network communications is described separately from the input/output interface 320 for local device communications, these two interfaces may be the same, or may share functionality, such as where a USB port 370 is used to attach to a Wi-Fi accessory, or where an Ethernet connection is used to couple to a local network attached storage. The input/output interface 320 may further output signals to displays of peripheral devices, as described herein.

As used herein, a user 330 is any human that interacts with the computer system 300. In this context, a user may be generally classed within one of two categories. One category is an administrator of the system, representing the financial institution organizing and conducting the offering of the multi-priced financing regime. Another category is an investor who buys and sells shares in the offering.

In certain embodiments the I/O interface 320 facilitates communication with input and output devices for interacting with a user. For example, the I/O interface may communicate with one or more devices such as a user-input device and/or a display 350 which may be instantiated on the device described herein or on a separate device such as a mobile device 208, which enable a user to interact directly with the controller 312 via bus 332. The user-input device may comprise one or more push-buttons, a touch screen, or other devices that allows a user to input information. In these embodiments, the computer system may further comprise a display to provide visual output to the user. The display may comprise any of a variety of visual displays, such as a viewable screen, a set of viewable symbols or numbers, and so on. One can appreciate that the inputs and outputs of the computer system would be different for administrators and investors. Accordingly, the computing device 310 may communicate administrators and investors with different interfaces 324 and 328.

A peripheral 322 may include any device used to provide information to or receive information from the computing device 310. This may include human input/output (I/O) devices such as a keyboard, a mouse, a mouse pad, a track ball, a joystick, a microphone, a foot pedal, a camera, a touch screen, a scanner, or other device that might be employed by the user 330 to provide input to the computing device 310. This may also or instead include a display, a printer, a projector, a headset or any other audiovisual device for presenting information to a user. The peripheral 322 may also or instead include a digital signal processing device, an actuator, or other device to support control of or communication with other devices or components. In one aspect, the peripheral 322 may serve as the network interface 316, such as with a USB device configured to provide communications via short range (e.g., Bluetooth, Wi-Fi, Infrared, RF, or the like) or long range (e.g., cellular data or WiMax) communications protocols. In another aspect, the peripheral 322 may augment operation of the computing device 310 with additional functions or features, such as another device. In another aspect, the peripheral 322 may include a storage device such as a flash card, USB drive, or other solid-state device, or an optical drive, a magnetic drive, a disk drive, or other device or combination of devices suitable for bulk storage. More generally, any device or combination of devices suitable for use with the computing device 310 may be used as a peripheral 322 as contemplated herein.

Other hardware 326 may be incorporated into the computing device 310 such as a co­processor, a digital signal processing system, a math co-processor, a graphics engine, a video driver, a camera, a microphone, additional speakers, and so forth. The other hardware 326 may also or instead include expanded input/output ports, extra memory, additional drives, and so forth.

A bus 332 or combination of busses may serve as an electromechanical backbone for interconnecting components of the computing device 310 such as the controller 312, memory 314, network interface 316, other hardware 326, data store 318, and input/output interface. As shown in the figure, each of the components of the computing device 310 may be interconnected using a system bus 332 in a communicating relationship for sharing controls, commands, data, power, and so forth.

The computing device 310 is connected to a power source 360 to provide electrical power for the computing device to run.

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a processor specially configured to perform the functions discussed in the present disclosure. The processor may be a neural network processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. Alternatively, the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described herein. The processor may be a microprocessor, controller, microcontroller, or state machine specially configured as described herein. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or such other special configuration, as described herein.

The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in storage or machine readable medium, including random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a device. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.

The processor may be responsible for managing the bus and processing, including the execution of software stored on the machine-readable media. Software shall be construed to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or specialized register files. Although the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

The machine-readable media may comprise a number of software modules. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a special purpose register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module. Furthermore, it should be appreciated that aspects of the present disclosure result in improvements to the functioning of the processor, computer, machine, or other system implementing such aspects.

If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any storage medium that facilitates transfer of a computer program from one place to another.

Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means, such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

The computer program controls input and operation of the device. The computer program includes at least one code segment stored in or on a computer-readable medium residing on or accessible by the device for instructing the computing element, and any other related components to operate in the manner described herein. The computer program is preferably stored within the memory and comprises an ordered listing of executable instructions for implementing logical functions in the device. However, the computer program may comprise programs and methods for implementing functions in the device that are not an ordered listing, such as hard-wired electronic components, programmable logic such as field-programmable gate arrays (FPGAs), application specific integrated circuits, or other similar or conventional methods for controlling the operation of electrical or other computing devices.

Similarly, the computer program may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device, and execute the instructions. The computer-readable medium may even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

Figure 4 shows a process flow diagram 400 for defining and offering for sale a first tranche of a multi-price share offering with incremental price increases according to an embodiment of the disclosed subject matter.

The process flow diagram 400 starts at block 402 wherein the computer system receives inputs from administrator(s) regarding a venture to be funded by a multi-price share sale as described herein. Inputs include a target amount of capital to be raised, information regarding the venture’s current assets, the current state and valuation of the venture and prospectus for obtaining new assets, etc.

The computer system determines a structure for the multi-price offering in block 404. The determination of the structure comprises conducting activities in blocks 210, 220 and 230 of Figure 2. It is to be appreciated that defining the structure of the offering in block 404 may comprise several iterative interactions between the computer system and administrator(s) to define the final structure of the offering.

Once the final structure of the offering is determined, the computer system moves to executing the offering (block 240 of Figure 2) by moving to block 406. Block 406 comprises offering the first tranche of shares in the first price category for sale to potential investors. Block 408 comprises receiving bids for shares from investors. Block 410 comprises accepting the bids from investors. Accepting the bids includes issuing shares to the investors at their bid price(s) and holding them in the computer system.

The system tracks the sales of shares in block 412, including the total number of shares sold and the prices offered in bids and accepted by the computer system. As the computer system tracks share sales it determines whether targets of the first tranche have been met in block 414. Targets may include shares in the first tranche being sold out, bid prices reaching a target price related to the offering price of the second tranche, target funding raised, time period for offering the first tranche expiring, or any combination thereof. If the target(s) are not reached, the computer system moves to block 416 to continue offering shares in the first offering, returning to block 408 and receiving more bids from investors.

If the computer system determines that the target(s) are reached in block 414, the computer system moves to block 418 and closes the first tranche. After closing the first tranche, the computer system moves to block 500 to open and offer a second (subsequent) tranche. As discussed above, the second tranche is offered at a higher price per share than the first tranche.

Figure 5 shows a process flow diagram for offering for sale of subsequent tranches of a multi-price share offering with incremental price increases. Figure 5 shows the process 500 for opening and offering for sale of the second tranche and any other subsequent tranches.

In block 502, the computer system announces the opening of the second or subsequent tranches, which includes setting the opening asking price of the tranche. In block 504, the computer system receives sell orders for shares bought in the prior tranches from owners of shares wishing to sell shares. When the tranche is the second tranche the first tranche is the prior tranche. When the subsequent tranche is the third tranche the first tranche and the second tranche are the prior tranches, etc. In block 506, the computer system add the shares designated in the sell orders in block 504 to the subsequent tranche for sale to new investors at the new increased sale price. New investors may include investors who had not participated in the prior tranche and/or investors in the prior tranche who wish to increase their holdings. In block 510, the computer system receives bids for shares from investors. Bids can be made for the shares from the prior tranche or from the current tranche. Block 512 comprises accepting the bids from investors. Bids for shares from prior tranches are accepted first, then bids for shares from the current tranche. Accepting the bids includes issuing shares to the investors at their bid price(s) and holding them in the computer system.

The system tracks the sales of shares in block 514, including the total number of shares sold and the prices offered in bids and accepted by the computer system. As the computer system tracks share sales it determines whether targets of the current tranche have been met in block 516. Targets may include shares in the prior and current tranche(s) being sold out, bid prices reaching a target price related to the offering price of a subsequent tranche, target funding raised, time period for offering the current tranche expiring, or any combination thereof. If the target(s) are not reached, the computer system moves to block 518 to continue offering shares in the tranche, returning to block 510 and receiving more bids from investors.

If the computer system determines that the target(s) are reached in block 516, the computer system moves to block 520 and closes the current tranche. After closing the current tranche, the computer system moves to block 522 to open and offer a subsequent tranche by returning to block 502 to announce opening of the subsequent tranche. As discussed above, the subsequent tranche is offered at a higher price per share than the current tranche. The process of opening and closing tranches summarized in process flow 500 is continued until all shares in all planned tranches are sold to investors. When all shares are sold, the computer system will end the process in block 520.

While the final tranche may be closed, the computer system may continue administering shares for the investors, allowing them to buy and sell shares within the system. If it is desirable to raise additional capital for the venture, the process flow may return to block 402 for the computer system to define a new tranche or tranches to be offered.

The system and methods described herein may be used for private offerings, initial public offerings or combinations thereof. For example, all tranches may be offered to a limited number of private venture capital entities. In other embodiments early tranches may be offered to a limited number of private venture capital entities, while later tranches may be offered in an initial public offering.